As a pseudo-random noise code generating circuit, by which it is possible to set codes and which is suitable for fabricating it in the form of an IC, there is known a circuit described e.g. in JP-A-No. 61-163088 and represented in FIG. 4. In FIG. 4 G.sub.1 .about.G.sub.n represent steering gate circuits, which can be constructed by using NAND gates. .sym. indicates an exclusive logical sum gate EOR.sub.1 .about.EOR.sub.n. SR.sub.1 .about.SR.sub.n are flipflops; AND.sub.1 .about.AND.sub.n are AND gates; L.sub.1 .about.L.sub.6 are latch circuits; MPX is a multiplexer; DE-MPX is a demultiplexer; INV.sub.1 and INV.sub.2 are inverters. As initial information necessary for the code generation by using a code generating device as indicated in FIG. 1 there are data determining each of the states (i).about.(iii) as indicated below;
(i) initial state of the flipflops; PA1 (ii) state of the feedback; and PA1 (iii) selection state of the last stage of the flipflops.
In FIG. 4 CLK represents a clock supplied to each of the flipflops SR.sub.1 .about.SR.sub.n ; STB a strobe for code exchange given to the steering gate G.sub.1 .about.G.sub.n ; and CS a chip selct signal; and LE a latch enable signal. DAT 0.about.n represent data (i).about.(iii) as indicated above and are given to the latch circuits L.sub.1 .about.L.sub.3. The output of the latch circuits L.sub.1 is given to each of the steering gates G.sub.1 .about.G.sub.n. The outputs of the latch circuits L.sub.2 and L.sub.3 are given to the AND circuits AND.sub.1 .about.AND.sub.n and to the mutliplexer MPX through the latch circuits L.sub.4 and L.sub.5, respectively. SEL 0.about.1 are data selects and select data as indicated in TABLE 1. The latch circuits L.sub.1 .about.L.sub.3 are controlled by the output of the demultiplexer DE-MPX and the latch circuits L.sub.4 and L.sub.5 are controlled by STB described previously. FB 0.about.2 and CAS are outputs used for connecting the circuit indicated in FIG. 4 in cascade. FB 2 is the three state output and PN is the code (pseudo-random noise code ) output.
TABLE 1 ______________________________________ SEL 1 SEL 0 Data ______________________________________ L L (i) L H (ii) H L (iii) H H meaningless ______________________________________
At first the operation, in the case where the circuit indicated in FIG. 4 is used alone, will be explained.
The feature of this system consists in that a desired long period code can be obtained easily by connecting a plurality of same circuits in cascade, when the circuit indicated in FIG. 4 is fabricated in the form of an IC.
However a circuit of this system fabricated in the form of an IC has a disadvantage that the highest working frequency is lowered by the cascade connection. FIGS. 5 (a) and (b) indicate the paths for which the transmission of signals takes the longest time in a prior art circuit fabricated in the form of an IC (hereinbelow called critical paths). FIG. 5 (a) indicates the critical path, in the case where the IC circuit described above is used alone and FIG. 5 (b) indicates same of an IC circuit IC.sub.1, in which two IC circuits described above are connected in cascade. The critical path, in the case where more than two IC circuits are connected in cascade, is identical to (b). In either case the fundamental construction of the critical path CL is SR.fwdarw.multiplexer.fwdarw.3 state output buffer.fwdarw.AND gate.fwdarw.EOR gate.fwdarw.steering gate.fwdarw.SR. However, when they are connected in cascade, since the signal propagates two times (A) and (B) outside of the IC circuits IC.sub.1 and IC.sub.2, the critical path becomes long. Since a buffer, an input protection resistor, etc. are necessary for the purpose of increasing the driving capacity, working out a countermeasure against static electric breakdown, etc. for the propagation of the signal between different IC circuits, the delayed time is considerably increased (corresponding to td in FIG. 5 (b).